High Level Synthesis Optimization of Scalable Video Codec Interpolators for Zynq SoC
High Level Synthesis Optimization of Scalable Video Codec Interpolators for Zynq SoC [...]
HLSTL (High Level Sintesis Template Library) Biblioteca para programación genérica sobre FPGA con HLS
HLSTL (High Level Sintesis Template Library) Biblioteca para programación genérica sobre FPGA [...]
Hierarchical Task Network planning with common-sense reasoning for multiple-people behaviour analysis
Hierarchical Task Network planning with common-sense reasoning for multiple-people behaviour analysis [...]
Non-linear classifiers applied to EEG analysis for epilepsy seizure detection
Non-linear classifiers applied to EEG analysis for epilepsy seizure detection Centre [...]
A semantic middleware architecture for supporting real smartness
A semantic middleware architecture for supporting real smartness Computer Architecture [...]
Early Detection of Hypoglycemia Events Based on Biometric Sensors Prototyped on FPGAs
Early Detection of Hypoglycemia Events Based on Biometric Sensors Prototyped on FPGAs [...]
HADA
Herramientas de Ayuda al Diseño de Sistemas Heterogéneos Complejos Project ID: TIC97-0928 Funded [...]
DOMOBOX
Dispositivo de control domótico Project ID: ARCO 01-99-00 Funded by: Telefónica I+D Type [...]
SENDA
Servicios y Redes para Aplicaciones Domóticas Project ID: 1FD972320 Funded by: European Regional [...]
DEMETER
Sistema de Televigilancia para Entornos Rurales y Espacios Protegidos Project ID: ARCO 02-02-03 [...]